Sumit Vaidya1 and Deepak Dandekar2
1Department of Electronic & Telecommunication Engineering, OM College of Engineering, Wardha, Maharashtra, India
2Department of Electronic Engineering, B. D. College of Engineering, Wardha, Maharashtra, India
Abstract
1Department of Electronic & Telecommunication Engineering, OM College of Engineering, Wardha, Maharashtra, India
2Department of Electronic Engineering, B. D. College of Engineering, Wardha, Maharashtra, India
Abstract
A typical processor central processing unit devotes a considerable amount of processing time in
performing arithmetic operations, particularly multiplication operations. Multiplication is one of the
basic arithmetic operations and it requires substantially more hardware resources and processing time
than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is
multiplication. In this paper, comparative study of different multipliers is done for low power requirement
and high speed. The paper gives information of “Urdhva Tiryakbhyam” algorithm of Ancient Indian
Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of
multipliers. Vedic Mathematics suggests one more formula for multiplication of large number i.e.
“Nikhilam Sutra” which can increase the speed of multiplier by reducing the number of iterations.
Keywords
Multiplier, Vedic Mathematics, VLSI design
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