Deewakar Thakyal and Pushpita Chatterjee
SRM Research Institute, Bangalore
ABSTRACT
The shortcomings of conventional bus architectures are in terms of scalability and the ever increasing
demand of more bandwidth. And also the feature size of sub-micron domain is decreasing making it
difficult for bus architectures to fulfill the requirements of modern System on Chip (SoC) systems. Network
on chip (NoC) architectures presents a solution to the earlier mentioned shortcomings by employing a
packet based network for inter IP communications. A pivotal feature of NoC systems is the topology in
which the system is arranged. Several parameters which are topology dependent like hop count, path
diversity, degree and other various parameters affect the system performance. We propose a novel
topology forNoC architecture which has been thoroughly compared with the existing topologies on the
basis of different network parameters.
KEYWORDS
Network on chip, Torus, Topology, NoC
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